The present invention relates to a boundary-scan circuit of an electronic device, and more particularly to a boundary-scan circuit to provide a reset signal between a reset input pin and a core logic reset input to reset the core logic in preparation for or at the completion of testing of the electronic device.
The integrated circuit industry has adopted IEEE Std. 1149.1 (1990), which is hereby incorporated by reference, to provide a standard test architecture for their products. The intent of the IEEE Std. 1149.1 standard is to provide compatibility of test control and data signals between devices from different manufacturers in much the same way that compatibility presently exists within major logic family, e.g. TTL, CMOS, etc. This standard test architecture facilitates the development of standard tests and standard test development techniques that may be reused instead of recreated every time a new electronic device is produced.
Many integrated circuits have reset input pins that are connected to their respective system or sub-system reset signals. If this system or sub-system reset signal is asserted, the core logic of the integrated circuit is asynchronously induced to a reset state. The reset state usually means that all memory devices, e.g. flip-flops, DRAMs, counters, etc., have their internal states reset to logic low levels. This causes the non- inverted outputs, i.e. the Q outputs, also to be at logic low levels. Those skilled in the art will appreciate that other definitions of a reset state are possible as long as the electronic device always assumes that predetermined state after a reset signal has been asserted at its reset input.
During various tests that are permitted under IEEE 1149.1, such as, boundary-scan testing, external testing (EXTEST) and built-in-self-test (BIST) testing, a reset pin may be functionally disconnected from the core logic that it resets in normal operation. This happens frequently during boundary-scan EXTEST testing and BIST testing of the core logic of the electronic device. This is necessary in order to permit the system test circuitry to test various conductor continuities and to provide stimulation of the core logic through numerous internal logic states. The resulting logic state at the end of a test may not have any individual significance to the test circuit as long as it corresponds to a correct response to an essentially random input. The resulting logic state, however, may have a totally different significance when the electronic device transitions from a test mode to normal operation. A random state which is an appropriate response in a test mode, may be decoded in normal operation as a very inappropriate command or data output by the electronic device when a transition is made from test mode to normal operating mode. Thus, there is a need to provide an apparatus and a method for placing the electronic device into a safe internal logic state whenever any type of testing of core logic or external connections is completed.
Thus, it is an object of the present invention to provide a boundary-scan circuit reset input circuit that switches from a system reset signal to a test reset signal before any other test signals can be communicated to core logic circuits of the circuit under test.
It is another object of the present invention to provide a boundary-scan reset input circuit that resets the core logic of the circuit under test after the test is completed and before the boundary-scan reset input circuit switches from the test reset signal to a system reset signal.
It is a further object of the present invention to provide a method for providing a test reset signal that resets the circuit under test to a safe final state after the completion of testing.